In digital computer systems, such as generically illustrated in FIG. 1, in block diagram form, system resources generally communicate with each other via one or more interconnections called buses. The system resources may include, for example, processors (1, 2 for example), memory (3, 4), and input/output devices (or their controllers) (5, 6, 7). The inter-resource communications generally involve multi bit (and usually multi-byte) information (i.e., data or command/response) transmission packets or packet sequences called transactions, which are exchanged via a bus 8. Only certain transactions are considered valid and are allowed; other potential transactions are screened out as invalid. Thus various rules are established for bus communications, to ensure, inter alia: (1) that only valid information is passed from one resource to another; (2) that only valid sequences of operations occur; and (3) that messages and information are properly delivered to their intended destinations. These rules are referred to as the protocol for the bus. While a considerable number of bus protocols exist, each with distinct advantages and disadvantages, most buses share at least one trait: they restrict the permissible bit sequences which can be transmitted on the bus preventing the transmission of some otherwise possible bit sequences.
Typically, a bus can only support at any given time only one or a small number of inter-resource communications. Thus, if a resource requires access to a bus and the bus is unavailable, that resource will have to wait until the bus later becomes available. To improve communications efficiency over a bus, and to allow system resources to perform useful work while the bus is being utilized by other resources, a technique known as transaction buffering frequently is employed. Transaction buffering is a process whereby each resource obtains access to the bus through a buffer, or buffer memory. One type of buffer often utilized for this purpose is a two-port RAM array. Such an array may, for example, embedded in a VLSI chip containing the circuitry for the associated system resource.
To ensure the integrity of the system, it is desirable to test such RAM array buffers from time to time. For example, it may be advantageous to test each RAM array when the system is "powered up", or when a malfunction must be diagnosed. The use of a RAM array as a bus transaction buffer, however, imposes certain obstacles in this respect. Specifically, the proper operation of a RAM array requires that random data be writeable to and readable from each and every bit of the array. As stated above, however, one thing most (if not all) bus protocols have in common is that they only permit certain bit patterns and sequences to be placed on the bus. In other words, bus protocols typically do not allow all possible bit patterns and sequences to be transmitted. For example, a protocol will typically reject as a destination a resource address which is not valid. Thus, a bus protocol usually will not allow the writing to a transaction buffer of a full range of random data in random order. The use of a bus protocol which screens out invalid transactions or information therefore will often also impede transaction buffer (i.e., RAM array) testing. Moreover, when there is a way to test a transaction buffer, it frequently will require that at least a portion of the system be deactivated, or halted -- that is, that system clocks be stopped and normal bus transactions be prevented.
Accordingly, it is an object of the present invention to provide, for use as a transaction buffer, a RAM array which is capable of being fully tested.
Another object of the invention is to provide a method for testing a RAM array transaction buffer without having to halt the system.
Still another object is to provide a method and apparatus for testing a RAM array transaction buffer without requiring any changes or special adaptations to the system bus and its protocol.